AArch64 MP+dmb.sy+addr-pos-[fr-rf]-addr-ctrlisb
"DMB.SYdWW Rfe DpAddrdR PosRR FrLeave RfBack DpAddrdR DpCtrlIsbdR Fre"
Cycle=Rfe DpAddrdR PosRR FrLeave RfBack DpAddrdR DpCtrlIsbdR Fre DMB.SYdWW
Relax=
Safe=Rfe Fre PosRR DMB.SYdWW DpAddrdR DpCtrlIsbdR [FrLeave,RfBack]
Prefetch=0:x=F,0:y=W,1:y=F,1:x=T
Com=Rf Fr Rf
Orig=DMB.SYdWW Rfe DpAddrdR PosRR FrLeave RfBack DpAddrdR DpCtrlIsbdR Fre
{
0:X1=x; 0:X3=y;
1:X1=y; 1:X4=z; 1:X9=a; 1:X11=x;
2:X1=z;
}
P0 | P1 | P2 ;
MOV W0,#1 | LDR W0,[X1] | MOV W0,#1 ;
STR W0,[X1] | EOR W2,W0,W0 | STR W0,[X1] ;
DMB SY | LDR W3,[X4,W2,SXTW] | ;
MOV W2,#1 | LDR W5,[X4] | ;
STR W2,[X3] | LDR W6,[X4] | ;
| EOR W7,W6,W6 | ;
| LDR W8,[X9,W7,SXTW] | ;
| CBNZ W8,LC00 | ;
| LC00: | ;
| ISB | ;
| LDR W10,[X11] | ;
Observed
z=1; y=1; x=1; 1:X6=0; 1:X5=1; 1:X3=1; 1:X10=1; 1:X0=1;